Contents
General Description
CD4027B is a dual JK flip-flop with a set terminal (SET) and clear terminal (RESET) and two output terminals of positive and negative phases. Triggered by the rising edge of the clock signal, both set and clear operations are active high. The CD4027 contains two monolithic integrated circuits with independent, complementary, and symmetrical J-K master-slave flip-flops. Each flip-flop provides J, K, set, reset, clock input, and buffered Q and Q non-output signals, respectively. The device can be used as a shift register, and by connecting the Q output to the data input, as a counter and flip-flop. When triggered on the rising edge of the clock, the logic level applied to the D input is transferred to the Q output. Set and reset are independent of the clock and are accomplished by a high level on the set or reset lines, respectively.
The CD4027B is useful when performing control, register, and switching functions. The logic levels of the J and K inputs and internal automatic controls control the state of each flip-flop; the change in the flip-flop state is synchronized with the positive transition of the clock pulse. The set and reset functions are clock independent and are initiated when a high signal occurs on the set or reset input.
Due to its superior performance and reliable quality, CD4027B is widely used for registers, counters, and control circuits.
CD4027B Pinout Configuration and Description
CD4027B Specification
Number of channels (#) – 2
Technology Family – CD4000
Supply voltage (Min) (V) – 3
Supply voltage (Max) (V) – 18
Input type – TTL
Output type – Push-Pull
Clock Frequency (MHz) – 12
ICC (Max) (uA) – 600
IOL (Max) (mA) – 1.5
IOH (Max) (mA) – -1.5
Features – Balanced outputs, Positive edge-triggered, Standard speed (tpd > 50ns), Positive input clamp diode, Preset, Clear
CD4027B Functional Block Diagram
Where to use CD4027B
Typical applications of CD4027B
CD4027 application circuit diagram (1): Photo-controlled relay switch circuit made with CD4027
The optical switch is made of double JK flip-flop integrated circuit CD4027. Typically a 555 chip would be used as the clock pulse, the circuit described here dispenses with this requirement. One of the two flip-flops in the CD4027 itself acts as a square wave oscillator.
CD4027 application circuit diagram (2): dual-channel sequential output switch circuit triggered by audio signal control (LM324\CD4027)
The sound is picked up by the electret microphone, which provides a good gain through the first and second op-amps of the four op-amps integrated circuit LM324. The third operational amplifier is configured as a level detector, and the non-inverting terminal amplifies and filters the signal output by the second op-amp. The inverting input of the third operational amplifier is connected to a voltage divider, and the reference voltage is given by a 10K resistor and a 4.7K potentiometer. The 100-ohm resistor ensures that the circuit triggers without error. Therefore, the sensitivity (threshold) of the circuit can be controlled by adjusting the potentiometer. Sensitivity control thus helps to reject any unwanted external sounds. The output of the level detector is a square wave pulse used to trigger the flip-flop. A 100uF capacitor connected to the power supply also helps avoid noise.
Since the circuit operates at 4.5V, digital circuits can be easily used. The circuit on the right can be used to control the direction of the DC motor. The circuit uses four NPN transistors and controls whether the transistors T1 and T4 are turned on or T2 and T3 are turned on through the CD4027 logic level. Filters connected to the circuit and tuned to different audio frequencies allow the same circuit to control multiple devices. For example, a high-frequency sound (such as a whistle) can switch device 1 and a low-frequency sound (such as clapping) can control device 2.
CD4027 application circuit diagram (3): nine-digit key combination lock circuit composed of CD4027
The nine-digit key combination lock as shown in the figure has a total of 9 keys, but there are only 4 valid keys, and the remaining 5 keys are pseudo keys. When the pseudo key is pressed, the circuit is reset, and the input of the previously pressed valid key is all invalid. The circuit composition is shown in the figure. The circuit consists of two dual JK flip-flops CD4027 and a dual four-input AND gate CD4082. Four of the two JK flip-flops are combined in parallel, and their respective CP terminals are connected to an effective button. Only by pressing the four effective buttons in sequence, can the AND gate output a high level to open the lock. If the pseudo key is pressed halfway, the circuit will automatically reset.
CD4027 Application Circuit Diagram (4): Ball Game Scorer (CD4027, CD4055, CD40192)
The circuit of the ball game scorer is shown in the figure, it is used to record and display the ball game results. The first nixie tube has only two states, that is, “off” or “1”, and the last two nixie tubes can display ten states from “0” to “9”, so the highest score of the scorer can reach 199 points. The circuit is mainly composed of the counter, decoding circuit, trigger circuit, display circuit, and an anti-jitter switch circuit.
